1. Field of the Invention
The invention relates to a writing method and system, and more particularly to a writing method and system for phase change memory.
2. Description of the Related Art
With the growth in the use of portable electronic devices, the desire for non-volatile memory has increased. Among the various kinds of non-volatile memory, phase change memory is the most competitive next generation non-volatile memory due to its high speed, low power consumption, high capacity, reliable, easy process integration and lower cost. Excessive driving current prevents the density of the phase change memory from being efficiently increased, thus diminishing competitiveness of phase change memory.
Recently, several solutions have been proposed to eliminate high driving current, these solutions include a new memory structure, such as an edge contact structure or a confined structure, and a new recording material, such as N-doped GST material or O-doped material. Another issue of incomplete crystalline or amorphous states exists, preventing correct increase or decrease in resistance of the phase change memory. The crystalline and amorphous states of phase change memory have dramatically different electrical resistivity values, and this forms the basis by which data are stored. The amorphous, high resistance state is used to represent a binary 0, and the crystalline, low resistance state represents a binary 1. If the difference between the resistances in the amorphous state and the crystalline state, i.e. the sensing margin, is not large enough, thus, the logic state of the phase change memory may not be correctly determined. Additionally, the incomplete crystalline and amorphous state also causes non-uniformity of the phase change memory. In order to solve the issue of the incomplete crystalline or amorphous states, the conventional solution increases the operating time of a SET operation and a RESET operation, power consumption is thus increased and the programming speed is decreased.
The SET and RESET operations are mainly achieved by inputting two current pulses with different current magnitude to the phase change memory to switch the phase change memory between the amorphous state and crystalline state. According to Ohm-Joule's Law, when the current is input to the phase change memory, the phase change memory is heated. The phase change memory may thus be crystallized or melted based on different current. Based on the described illustration, the logic state of the phase change memory can be switched by inputting different currents, enabling data storage. FIG. 1 is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory. When a RESET operation is applied to the phase change memory, a reset current IRESET with high amplitude and short pulse width is applied, the phase change memory is thus melted because the temperature of the phase change memory exceeds the melting temperature of the phase change material of the phase change memory, Tm. When the temperature of the phase change memory decreases, the state of the phase change memory is transformed to the amorphous state due to the insufficient cool down period. Thus the phase change memory has high resistance. When a SET operation is applied to the phase change memory, a set current ISET with lower amplitude and longer pulse width is applied. The phase change memory is heated by the set current ISET, and the temperature of the phase change memory is held substantially between the melting temperature Tm and a crystallizing temperature Tc of the phase change material used by the phase change memory. During the SET operation, the melted phase change memory has sufficient time for crystallizing and the phase change memory thus has a low resistance.
As described, the phase change memory respectively stores data with logic state 1 and 0 by the RESET operation and the SET operation. When reading the phase change memory, a read current IREAD the amplitude of which less than the set current ISET, is applied to the phase change memory to determine the logic state of the data stored in the phase change memory.
With the novel phase change memory development technique, the size of the phase change memory cell is reduced. When the size of the phase memory cell is reduced, the SET operation of phase change memory cell becomes problematic. The SET operation of the memory cell may result in incomplete crystallization of part of the active area of the memory cell, increasing the resistance of the memory cell and the sensing margin of the memory cell is reduced. Additionally, the incomplete crystalline and amorphous states also cause non-uniformity of the phase change memory. In order to solve the issue of the incomplete crystalline and amorphous states, the conventional solution increases the duration of the SET operation, i.e. increasing the SET pulse width, but the power consumption is increased. The memory may be overheated and the programming speed of the memory is decreased.